The present invention relates, in general, to the testing of circuits, and, more specifically to the testing of very large and/or very fast integrated circuits and to circuits adapted for use with the method.
Multi-cycle paths have been and continue to be perceived as a fundamental problem for Built-In Self-Test (BIST) because most BIST schemes cannot handle multi-cycle paths. A multi-cycle path is a timing path through a combinational circuit that requires more than one clock period to traverse. Multi-cycle paths can be deliberate or accidental. In the design of certain types of functionality, it is useful to intentionally incorporate multi-cycle paths into a chip design. For example, synchronous counters which utilize multi-cycle paths can run at a higher frequency compared to counters constructed with the same technology but without multi-cycle paths. An accidental multi-cycle path is similar to a deliberate multi-cycle path except that the designer is usually not aware of multi-cycle paths without running static timing analysis. An example of an accidental multi-cycle path is a mode signal transmitted from one module to another. If the chip is not required to function correctly on the clock cycle immediately after the mode signal has been changed, the designer might not have simulated this mode transition and realized that the path is a multi-cycle path.
In typical scan testing schemes, pseudo-random test patterns are loaded or shifted into scannable memory elements. The output response of the circuit is captured in the memory elements, shifted out of the elements and compacted into what is referred to as a xe2x80x9csignaturexe2x80x9d. The signature is compared to a reference signature, on chip or in an external tester, and a pass/fail test result is obtained. When the test stimulus is applied, it is expected that all data will traverse all logic paths and meet flip-flop setup time requirements of the capture clock during the period(s) where an at-speed test is performed, i.e., the test stimulus is launched from memory elements consequent to a first active clock edge and the output response is captured consequent to a second active clock edge, the time period between the clock edges being substantially the same as that used during the normal operation of the circuit. This requirement cannot always be satisfied for multi-cycle paths. The signature obtained from circuits having multi-cycle paths is dependent on the test frequency used to perform the test. If the clock rate of the test clock is sufficiently low, the correct signature is always obtained in a properly functioning circuit because the slow clock rate allows sufficient time for the output of the memory elements which source multi-cycle paths to settle before the capture cycle. However, a different signature may be obtained when a higher test clock rate is used. Clearly, frequency-dependent variation in the test response of a circuit is unacceptable. Useful tests require testing the circuit at the normal operation clock rate of the circuit. It is when attempts are made to test a circuit at-speed, i.e. at the speed for which the circuit was designed to operate during normal operation, that problems arise.
Nadeau-Dostie et al U.S. Pat. No. 6,145,105 granted on Nov. 7, 2000 for xe2x80x9cMethod and Apparatus for Scan Testing Digital Circuitsxe2x80x9d, which is incorporated herein by reference, proposes a method by which both shift and capture operations are performed at-speed. Memory elements which source multi-cycle paths are arranged in separate scan chains with other memory elements with the same output propagation delay. The test is performed at-speed. All memory elements that source values into multi-cycle paths are made to shift at a slower frequency, which means that they are stable for a number of clock cycles, corresponding to the propagation delay in the path, before the capture edge. The multi-cycle path source memory elements are provided with an extra 2-to-1 multiplexer, which allows shifting at a lower frequency without affecting its clock connection. By reducing the shift rate, the time from the last shift clock to the capture clock is increased relative to that of a higher shifting rate, providing enough time for multi-cycle paths to settle before the capture edge of the capture cycle. The method provides consistent signatures at different test clock rates. However, the scan enable signal, which configures scannable memory elements in shift and capture modes, becomes a timing critical signal which must be distributed to all scannable memory elements within one system clock cycle. Even though the scan enable signal can be pipelined, as shown in Nadeau-Dostie et al, there might still be difficulty distributing the signal in time in very large and/or very fast circuits. For such circuits, an alternative method is required.
The present invention seeks to provide an improved scan testing method which can be used in circuits having multi-cycle paths with various propagation delays, and in very large and/or very fast circuits in addition to conventional circuits. In the present invention, the state of memory elements which source multi-cycle paths is controlled independently of non-source memory elements during capture operations so that, depending on the clock rate used during capture operations and the propagation delay through the combinational logic in its output, source memory elements are either configured in capture mode throughout the capture operation or in hold mode for all but the last cycle of the capture operation when it is configured in capture mode.
In accordance with one aspect of the present invention, there is provided a method for at-speed testing of a circuit having combinational logic and scannable memory elements connected to the combinational logic, with one or more of the memory elements being a source of a multi-cycle signal path having a propagation delay that is longer than the period of a system clock applied to the elements during normal operation of the circuit, each source memory element having a predetermined maximum capture clock rate, corresponding to a minimum capture clock period, within which the output of a source element can traverse the signal path within one cycle of the capture clock, the scannable memory elements being configurable in shift mode and capture mode, the source memory elements being additionally configurable in hold mode, the scannable memory elements being clocked by a common clock signal, the method comprising loading a test stimulus into the scannable memory elements; performing a capture operation including configuring in capture mode throughout the capture operation non-source memory elements and source memory elements having a predetermined maximum capture clock rate which is the same as or higher than the clock rate of a capture clock; and configuring in a hold mode during all but the last cycle of the capture clock and in capture mode for the last cycle thereof, source memory elements having a predetermined capture clock rate which is lower than the clock rate of the capture clock; applying at least two clock cycles of the capture clock; and unloading test response data captured by the scannable memory elements.
Controlling source memory elements in this manner during the capture operation ensures that the outputs of the source memory elements reach their respective destinations prior to the capture cycle, including when the test is performed at speed, and thus ensures that the signatures obtained are independent of the clock rate used to perform a test. A further aspect of the method of the present invention involves specifying a clock code indicating a desired capture clock rate and a burst length code indicating the number of clock cycles to be provided during the capture operation.
In accordance with another aspect of the invention, there is provided a test controller for use in at-speed scan testing of a circuit having combinational logic and scannable memory elements including memory elements which source multi-cycle signal paths having propagation delays that are longer than the period of a system clock used during normal operation of the circuit, each source memory element having a predetermined maximum capture clock rate within which the output thereof can traverse the signal path within one cycle of an input clock, the scannable memory elements being configurable in shift mode and capture mode, the source memory elements being configurable in shift mode, capture mode and hold mode, the test controller comprising a clock generating circuit for generating a common clock signal for the scannable memory elements, the clock generating circuit providing a shift clock rate during test stimulus loading and test response unloading operations; and a capture clock rate derived from a system clock during capture operations; and a source memory element control circuit for configuring in capture mode throughout a capture operation source memory elements having a predetermined maximum capture clock rate which is the same as or higher than the desired capture clock rate; and configuring in a hold mode during all but the last cycle of the capture operation and in capture mode for the last cycle thereof, source memory elements having a predetermined capture clock rate which is lower than the desired capture clock rate.
As is known in the art, integrated circuit devices are typically designed and fabricated using one or more computer data files, referred to herein as hardware definition programs or circuit description, that define the layout of the circuit arrangements on the devices. The programs are typically generated by a design tool and are subsequently used during manufacturing to create the layout masks that define the circuit arrangements applied to a semiconductor wafer. Typically, the programs are provided in a predefined format using a hardware definition language (HDL) such as VHDL, verilog, EDIF, etc. While the invention has and hereinafter will be described in the context of fully functioning integrated circuit devices and data processing systems utilizing such devices, those skilled in the art will appreciate that the various embodiments of the invention are capable of being distributed as a program product in a variety of forms, and that the invention applies equally regardless of the particular type of signal bearing media used to actually carry out the distribution. Examples of signal bearing media include but are not limited to recordable type media such as volatile and non-volatile memory devices, floppy disks, hard disk drives, CD-ROM""s, and DVD""s, among others and transmission type media such as digital and analog communications links. Another aspect of the present invention relates to a software tool or program product for modifying an existing circuit description so as to incorporate into it scan testing capability according to the present invention.
In accordance with still a further aspect of the present invention, there is provided a method and program product for modifying a circuit description so as to adapt the circuit for at-speed testing, the circuit having combinational logic and scannable memory elements, including scannable memory elements having an output which is a source of a multi-cycle signal path having a propagation delay that is longer than the period of a system clock used during normal operation, the scannable memory elements having a clock input used during both the functional mode of operation and a shift mode of operation, the method comprising reading a circuit description of the circuit having a description of each scannable memory element; inspecting the description of each scannable memory element and determining the propagation delay of the output of the scannable memory element, and, when the propagation delay is greater than one cycle, arranging the scannable memory element in a multi-cycle path group of scannable memory elements having the same propagation delay to receive the same control signal; and revising the description of the scannable memory element by adding a hold mode defined by a control signal; inserting into the circuit description, a description of a test controller for performing at-speed testing of the circuit, including: inserting a description of a clock generating circuit for generating a common clock signal applied to the clock input of the memory elements during testing of the circuit, in which the common clock signal comprises shift clock signal derived from a test clock signal, a capture clock signal derived from a system clock signal in which the number of cycles of the capture clock is determined from a combination of a burst length signal and the capture clock rate is determined from a clock code signal; and inserting a description of a clock enabling circuit for generating a group clock enable signal for each multi-cycle group of scannable memory elements; and storing the revised description of the circuit.